1. Field of the Invention
The present invention relates generally to an AFC (automatic frequency control) method and a receiving apparatus using it, and more particularly, to a method for improving the accuracy of AFC and a receiving apparatus using the improved AFC method.
2. Description of the Background Art
In satellite broadcasting which is currently carried out in Japan, a video signal of the NTSC (National Television System Committee) standard is FM-modulated to be transmitted as an FM video signal of 12 GHz band.
On the receiving side, this FM video signal of 12 GHz band is converted into a first intermediate frequency signal of 1 GHz band, and further down-converted into a second intermediate frequency signal of the frequency band including 134.26 MHz, and 402.78 MHz. Thereafter, the second intermediate frequency signal is FM-demodulated so that a video signal is supplied as an output.
The oscillation frequency of a local oscillator for a down-conversion is satisfactorily controlled by an AFC circuit (automatic frequency control circuit). A plurality of circuits constitute an AFC loop, to perform an AFC operation. Ordinary AFC utilizes the fact that the level of a direct current signal in a synchronizing signal portion of the video signal outputted from an FM modulator corresponds to the frequency of the second intermediate frequency signal. Thus, in the ordinary AFC, this level of the direct current signal is detected and the results of this detection is fedback, thereby to control the oscillation frequency of the local oscillator (see U.S. Pat. No. 4,417,279).
However, the direct current signal has the disadvantage of being susceptible to a drift or the like. Therefore, a technique is developed in which the frequency of the second intermediate frequency signal (hereinafter referred to as second IF signal) is counted, and the count data obtained by the counting discounting is fedback to control the frequency of the local oscillator.
Referring to FIGS. 1 and 2, this example will be briefly described.
In FIG. 1, a BS (broadcasting satellite) antenna 10 comprises an antenna portion 11 and a first converter 12. The antenna portion 11 is, for example, a parabolic antenna or a plane antenna. The first converter 12 comprises an oscillator 13 and a mixer 14. In the first converter 12, a satellite broadcasting signal (FM video signal) of 12 GHz band received by the antenna portion 11 is mixed with an output of the oscillator 13 by the mixer 14. Consequently, an FM video signal (first intermediate frequency signal) (hereinafter referred to as first IF signal) of approximately 1 GHz band is supplied as an output. Fluctuations in the frequency of the first IF signal is allowed to .+-.1.5 MHz. The fluctuations are corrected by an AFC operation.
A BS tuner 16 comprises a second down-converter 18, a PLL (Phase Locked Loop) circuit 30, a microcomputer 32 for channel selection, an FM demodulating block 34, a counter circuit 46, an output processing block 64, and a synchronizing separator circuit 68.
The second down-converter 18 converts a first IF signal into a second IF signal advantageous for a multi channel, for example, of 402.78 MHz band. The second down-converter 18 comprises amplifiers 20 and 24 for automatic gain control, a mixer 22, a variable oscillator 26, and prescaler 28 for dividing the frequency into 1/2.
The PLL circuit 30, together with the variable oscillator 26 and the prescaler 28, constitutes a PLL. The microcomputer for channel selection 32 switches a frequency dividing ratio of a program divider contained in the PLL circuit 30 to switch a receiving channel, and performs an AFC operation for fine tuning. Meanwhile, a general PLL is well known, which is disclosed in, for example, Japanese Patent Laying-Open No. 60-77533.
The FM demodulating block 34 comprises a second IF filter 36, an amplifier 38, a PLL type FM demodulator 40, an AGC detector 42 for generating an AGC voltage, and a 1/256 frequency divider 44 made of ECL.
The counter circuit 46 directly counts an output signal of the 1/256 frequency divider 44. The period of resetting and counting operations of the counter circuit 46 is controlled by the microcomputer 32. Count data obtained by the counter circuit 46 is supplied to the microcomputer 32.
The output processing block 64 comprises a sound DPSK signal demodulator 48, a PCM decoder 50, a sound output circuit 52, an encoder 54 for a digital equipment output, a buffer amplifier 56, a low-pass filter/deemphasis circuit 58, a disversal circuit 60 for removing a triangular wave, and an output amplifier 62.
The PCM decoder 50 is, for example, TM4218N made by Toshiba corporation, which comprises a terminal 50a from which an NSYNC signal is outputted at the time of receiving a sound PCM signal in NTSC broadcasting. The sound output circuit 52 comprises a D/A converter for converting digital signals into analogue signals and a low-pass filter.
Furthermore, the BS tuner 16 comprises a group 66 of output terminals. The group 66 of output terminals comprises terminals 66a, 66b for sound output, output terminals 66c and 66d of the DAT optical cable connecter specifications, an output terminal 66e for a bit stream, an output terminal 66f for a subscription broadcasting decoder, and a video signal output terminal 66g.
The synchronizing separator circuit 68 extracts a vertical synchronizing signal V.sub.D, to output the same to the microcomputer 32.
Description is made of an operation of the above described BS tuner 16.
In the BS tuner 16, the counter circuit 46 is operated in a predetermined time period, and the count data obtained by the counter circuit 46 is inputted to the microcomputer 32. The microcomputer 32 compares the count data with a predetermined reference data, thereby to detect the deviation in the frequency of the second IF signal. The microcomputer 32 changes the frequency dividing ratio of the program divider included in the PLL circuit 30 so as to correct the deviation.
The microcomputer 32 determines a predetermined period during which a counting operation is performed by the counter circuit 46 based on the vertical synchronizing signal V.sub.D. This predetermined period is shown in FIG. 2.
In FIG. 2, (a) indicates an output of the PLL type FM demodulator 40, (b) indicates an output of the synchronizing separator circuit 68, (c) indicates a clear signal c1 outputted from the microcomputer for the counter circuit 46, and (d) indicates a gate signal "gate" outputted from the microcomputer 32 for designating the period during which the counting operation is performed by the counter circuit 46.
When the vertical synchronizing signal V.sub.D is inputted to the microcomputer 32 from the synchronizing separator circuit 68, the microcomputer 32 outputs the clear signal c1. At the same time, the microcomputer 32 outputs the gate signal "gate" in the vertical synchronization blanking period A (for 1024.mu. seconds), to allow the counting operation of the counter circuit 46. Thereafter, the microcomputer 32 ceases output of the gate signal "gate" in a period B and then, outputs the gate signal "gate" again in a period C of 1024.mu. seconds. The microcomputer 32 reads the count data obtained by the counter circuit 46 in a subsequent period D. In order to remove the effect of the triangular wave which is an energy diffusion signal, the microcomputer 32 compares a value obtained by adding four results of counting in a two frame period and dividing the results of the addition by 4 with the value of the reference data at the time of receiving NTSC broadcasting, to detect deviation in the frequency of the second IF signal. The microcomputer 32 adjusts the frequency dividing ratio of the PLL circuit 30 based on the deviation. In the above described manner, the AFC operation is performed.
In addition, the value of the period B in (d) in FIG. 2 is changed for each field to, for example, 6 m seconds, 4 m seconds, 6 m seconds and 8 m seconds, so that the value of the frequency in each portion on the screen is detected. Consequently, fluctuations caused by variation in brightness are prevented.
The microcomputer 32 controls the PLL circuit 30 for each two frame period to perform a mean value AFC operation. When the PLL circuit 30 is controlled for each field, the previous four results of counting may be averaged and the mean value may be compared with the values of the reference data, to perform the AFC operation.
Furthermore, although in the above described example, four results of counting in a four field (2 frames) period are averaged, it should be noted that the present invention is not limited to the same. For example, results of counting in a four-, six- or eight-frame period may be averaged.
As stated above, in each field, the reason why the counter circuit 46 is operated in the vertical blanking period A and any period B in the video signal period will be described in the following.
Essentially, a frequency level and a pedestal level of a vertical synchronizing signal in a vertical blanking period should be each constant all the time. Therefore, in order to perform an AFC operation, it is only necessary to detect the frequency level in the vertical blanking period A. However, if the counting operation is performed only in the vertical blanking period A, there is a possibility that a malfunction might be caused by a noise or the like. Therefore, the counter circuit 46 is also operated during any period B in the video signal period in addition to the vertical blanking period A.
A counting operation is also performed in the period B in order to cause the counting operation to correspond to the mean value AFC on the transmission side.
However, even though the methods described above were used, in fact, it was impossible to perform an AFC operation precisely. The cause thereof was not made clear, either.
A method has also been proposed in which a counting operation is performed within a period of one cycle of the energy diffusion signal (1/15 seconds). Such a method is disclosed, for example, in National Technical Report, Vol. 34, No. 5, Oct. 1988, pp. 54-61.
However, to implement this method, an additional frequency divider or a large-scale counter is needed.